Elevated source/drain field effect transistor and method for making the same

ABSTRACT

A gate oxide film ( 23 ), a gate electrode ( 24 ) and a gate cap insulating film ( 25 ) are stacked on an active region of a p-type semiconductor substrate ( 21 ), and an insulating side wall ( 29 ) is formed, followed by BF 2  ion implantation. Thus, a surface of the p-type semiconductor substrate becomes amorphous so that single-crystal silicon is prevented from epitaxially growing in the next process of depositing polysilicon ( 33 ). Halo regions ( 32 ) are formed using the BF 2  ions having the opposite conductivity to a source/drain to reduce the short-channel effect. The substrate is then passed through a nitrogen purge chamber having a dew point kept at −100° C. to remove water molecules completely, and polysilicon ( 33 ) is deposited. Because native oxide is prevented from growing at an interface between the active region and the polysilicon, source/drain regions ( 34 ) formed later by implantation and diffusion of n-type impurity ions achieve a uniform junction depth.

This application is the national phase under 35 U.S.C. §371 of PCTInternational Application No. PCT/JP00/06046 which has an Internationalfiling date of Sep. 6, 2000, which designated the United States ofAmerica.

TECHNICAL FIELD

The present invention relates to a method for producing a semiconductordevice and a semiconductor device produced by the method. Moreparticularly, it relates to a source/drain elevated type FET (fieldeffect transistor) capable of suppressing a short channel effect andincreasing a current drive power, and a production method therefor.

BACKGROUND ART

In recent years, as the gate lengths of MOS (metal oxide semiconductor)FETs get shorter, the so-called short-channel effect represented byrapid lowering of the threshold voltage has become a problem. In orderto suppress the short-channel effect, the source/drain regions have beenrequired to have a shallower depth of junction. However, a merereduction in the depth of the source/drain regions would increase theresistance of these regions. Therefore, a source/drain elevated typetransistor wherein source/drain regions are elevated higher than asurface of the substrate has attracted attention. This structure makesit possible to provide the source/drain regions with their junctionsbeing substantially shallow and with their electrical resistances beinglow.

FIG. 6 shows a process for fabricating a conventional source/drainelevated type transistor. First, as shown in FIG. 6(a), a gate electrode3 is formed on a semiconductor substrate 1 with an oxide film 2interposed therebetween, and then a gate cap insulating film 4 is laidthereon according to a conventional process. Then, insulating sidewalls5 are formed on side surfaces of the gate electrode 3. A referencenumeral 6 indicates an element isolation region.

Subsequently, as shown in FIG. 6(b), a silicon film 7 is selectivelygrown between the sidewall 5 and the element isolation region 6 on thesemiconductor substrate 1, so that the silicon films 7, which are tobecome source/drain regions later, are thereby elevated on the surfaceof the semiconductor substrate 1. After that, as shown in FIG. 6(c), asource/drain impurity is implanted into the silicon films 7 to formsource/drain regions 8. In addition, the impurity is diffused into thesilicon substrate 1 by thermal treatment, thus making the source/drainregions 8 present within the semiconductor substrate 1 as well. Thereby,the source/drain elevated type transistor is formed.

However, the conventional source/drain elevated type transistor has thefollowing drawbacks. That is, when forming the source/drain 7 on thesurface of the semiconductor substrate 1, single-crystal silicon isepitaxially grown. During the growth, facets 10 are produced at aboundary between the insulating sidewall 5 and the silicon film 7 and ata boundary between the element isolation region 6 and the silicon film7. Due to the presence of the facets 10, impurities are deeply implantedinto both end portions of each source/drain region 8 within thesemiconductor substrate 1, as shown in FIG. 6(c), resulting in a problemin that the formation of a shallow junction is very difficult.

Further, surfaces of the elevated source/drain regions are silicified inorder to reduce their electrical resistances. In that case, at endportions of the gate electrode where the elevated layers are thin, asilicide is formed even within the semiconductor substrate 1, and thusthere is a problem that junction characteristics deteriorate.

As described above, when the source and drain 7 are elevated accordingto the conventional process, the facets 10 are produced, and thus it isvery difficult to form favorable junctions. Then, as a solution toreduce the influence of the facets 10, there is a method by which thefacets 10 are filled with polysilicon and the like as disclosed inJP-A-11-74507, for example. However, steps such as deposition ofpolysilicon and etch back are required. Thus, there is a problem thatthe production process becomes complicated.

Furthermore, since single-crystal silicon is used for forming theelevated source and drain 7, there are not only the facets 10-relatedproblem but also a problem that, in correspondence withproduction-attributed variations in the thickness of the single-crystalsilicon film 7, there are variations in the junction depths of thesource/drain regions 8 in the semiconductor substrate 1. The problem ofthe variations in the junction depths of the source/drain regions 8,which is attributed to the variations in the thickness of thesingle-crystal silicon films 7, can be solved by depositing polysiliconin place of single-crystal silicon. This is because polysilicon does notproduce a facet during deposition and moreover, the impurity diffusioncoefficient of polysilicon is larger than that of single-crystalsilicon. Accordingly, the variations in the thickness of the depositedpolysilicon film between products hardly affect the junction depths ofthe source/drain regions.

However, if equipment from which oxygen is sufficiently eliminated isnot used in the deposition of polysilicon, a nonuniform native oxidefilm is produced between the semiconductor substrate and the polysiliconfilm thus deposited. This native oxide film becomes a diffusion barrieragainst source/drain impurities implanted later. For that reason, thereis a problem that a good junction cannot be obtained. Accordingly, thedeposition of silicon must be performed under the condition that oxygenis sufficiently eliminated. However, in the case where oxygen issufficiently eliminated, without any surface treatment performed on thesemiconductor substrate, polysilicon would inherit the crystalorientation of the semiconductor substrate and epitaxially grow, thuscausing another problem that a desired polysilicon film cannot beobtained.

DISCLOSURE OF INVENTION

An object of the invention is to provide a method for producing asource/drain elevated type semiconductor device, which method candeposit a polycrystalline conductive film, such as polysilicon, thatfavors achievement of a shallow source/drain junction depth, and also toprovide a semiconductor device produced by the production method.

In order to accomplish the above object, a method for producing asemiconductor device according to the present invention comprises thesteps of:

sectioning a surface of a substrate or well region of first conductivetype to form an active region and then forming a gate oxide film on theactive region;

forming a gate electrode on the gate oxide film;

forming insulating sidewalls on side surfaces of the gate electrode;

implanting ions into a surface of the semiconductor substrate or wellregion at portions of the active region that are to be source/drainregions, to thereby make these portions amorphous;

depositing a polycrystalline conductive film on the surface of thesemiconductor substrate or well region formed with the gate oxide film,the gate electrode and the insulating sidewalls;

performing etch back on the polycrystalline conductive film to formconductive sidewalls on side surfaces of the insulating sidewalls;

implanting high-concentration impurities of second conductive type intothe conductive sidewalls; and

diffusing the high-concentration impurities of second conductive typeinto the semiconductor substrate or well region by a thermal treatmentto thereby form the source/drain regions.

With the above constitution, since the surfaces of the portions tobecome the source and drain regions in the active region of the firstconductive type semiconductor substrate or well region are madeamorphous, a monocrystal conductive film will not epitaxially growduring the deposition of a polycrystal conductive film on the surface ofthe semiconductor substrate or well region, but a desiredpolycrystalline conductive film without any facets is deposited.Therefore, in the case where the semiconductor substrate or well regionis a single-crystal semiconductor substrate, utilizing the differencebetween the impurity diffusion coefficient of the polycrystallineconductive film and that of the single-crystal semiconductor allows auniform junction depth of the source/drain regions in the semiconductorsubstrate or well region to be set.

In one embodiment, the ions implanted into the surface of the activeregion are of the first conductive type and at an impurity concentrationhigher than that of the first conductive type semiconductor substrate orwell region.

With the above constitution, when the surface of the semiconductorsubstrate or well region is made amorphous, the first conductive typeions are implanted at an impurity concentration higher than that of thefirst conductive type semiconductor substrate or well region. Thus, partof the ion-implanted regions form halo regions. Accordingly, theshort-channel effect is suppressed by the halo regions.

Preferably, the deposition of the polycrystalline conductive film may becarried out in an ambient having an oxygen concentration of 1 ppm orlower.

With this constitution, an oxide film is not formed at the interfacebetween the semiconductor substrate or well region and the conductivesidewalls. Thus, when the source/drain regions are formed later, thesecond conductive type high-concentration impurities are thermallydiffused into the semiconductor substrate or well region smoothly. As aresult, the junction depth of the source/drain regions in thesemiconductor substrate or well region is more uniformly set.

Further, a semiconductor device according to the present inventioncomprises a gate insulating film and a gate electrode stacked in thisorder on a substrate or well region of first conductive type, sidewallinsulating films disposed on side surfaces of the gate electrode, achannel region formed in the semiconductor substrate or well regionbeneath the gate electrode, and source/drain regions of secondconductive type elevated up to above the semiconductor substrate or wellregion from both sides of the channel region, the source/drain regionsbeing electrically isolated from the gate electrode by the gateinsulating film and the sidewall insulating films, and is characterizedin that the semiconductor substrate or well region has diffusion regionsof the first conductive type formed between the source/drain regions andthe channel region, the diffusion regions having an impurityconcentration higher than that of the semiconductor substrate or wellregion.

The source/drain regions of this semiconductor device are elevated up toabove the semiconductor substrate or well region from both the sides ofthe channel region in the first conductive type semiconductor substrateor well region. Therefore, when implanting the second conductive typehigh-concentration impurities into the source/drain regions in theformation of the source/drain regions, a shallow junction is formed inthe semiconductor substrate or well region.

Furthermore, the first conductive type diffusion layer regions having animpurity concentration higher than that of the semiconductor substrateor well region are present surrounding the source/drain regions. Forthat reason, extension of a depletion layer is suppressed whereby theshort-channel effect is suppressed.

If the impurity concentration of the first conductive type diffusionlayer regions falls in the range of 5×10¹⁷/cm³-1×10¹⁹/cm³, morefavorable suppression of the short-channel effect is achieved.

In one embodiment, the source/drain regions on the surface of thesemiconductor substrate or well region are delimited by elementisolation regions, and the elevated source/drain region on thesemiconductor substrate or well region has, on an upper side thereof, alength in a transistor gate length direction that is longer than adistance between the sidewall insulating film and the element isolationregion.

With this constitution, the capacitance between each of the source/drainregions and the semiconductor substrate or well region is greatlyreduced resulting in an improvement in the operation speed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a process flow chart which shows one example of the process ofproducing a semiconductor device of this invention;

FIG. 2 is an explanatory view showing that native oxide is formed at aninterface between a surface of an active region and a polysilicon film;

FIG. 3 is a sectional view of an n-channel MOSFET fabricated by themethod for producing a semiconductor device shown in FIG. 1;

FIG. 4 is a sectional view of a conventional n-channel MOSFET having nohalo region;

FIG. 5 is a sectional view of an n-channel MOSFET different from FIG. 3;and

FIG. 6 is a process flow chart which shows a process for fabricating aconventional source/drain elevated type transistor.

BEST MODE FOR CARRYING OUT THE INVENTION

This invention will be explained in more detail by way of the followingembodiments illustrated in the drawings.

First Embodiment

FIG. 1 shows a process for producing an n-channel MOSFET as asemiconductor device according to the present embodiment. The presentembodiment is also applicable to a method of producing a p-channelMOSFET in addition to the n-channel MOSFET. The method of producing ann-channel MOSFET will be hereinafter explained with reference to FIG. 1.Although FIG. 1 and the rest of the drawings are all sectional views,hatching has been omitted to make the drawings simple.

First, as shown in FIG. 1(a), element isolation regions 22 are formed ona p-type semiconductor substrate (silicon substrate) (or a p-type wellregion of a semiconductor substrate) 21, so that the substrate 21 issectioned or partitioned to form active regions surrounded by theelement isolation regions 22. In a case where the reference numeral 21denotes not the p-type semiconductor substrate 21 but a p-type wellregion of a substrate, the p-type well region is formed to a depth ofabout 1 μm at an impurity concentration of, for example,5E16/cm³-1E18/cm³, namely, 5×10¹⁶/cm³-1×10¹⁸/cm³. Further, in a casewhere a CMOS (complementary metal oxide film semiconductor) is formedusing the n-channel MOSFET, a well region having the oppositeconductivity to that of source/drain regions may be additionally formedin the p-type semiconductor substrate 21.

After that, a gate oxide film 23 (a nitride oxide film 2.5 nm thick), agate electrode 24 (a polysilicon film 200 nm high and 0.15 μm wide [gatelength]) and a gate cap insulating film 25 (a silicon oxide film 150 nmthick, which is not limitative) are stacked on the active region in thisorder. Next, a silicon oxide film 26 having a film thickness of about 10nm is formed on side surfaces of the gate electrode 24 by oxidationthereof, and then an insulating film 27 made of a silicon nitride filmor the like is deposited on the entire surface (to a film thickness of60 nm). Thereafter, except for the gate region and its proximity, aresist film 28 is formed in order to protect the p-type semiconductorsubstrate 21 and the element isolation regions 22 from damage due to thefollowing etching process. After that, the insulating film 27 is etchedback thereby forming insulating sidewalls 29 and insulating films 30 forprotecting the p-type semiconductor substrate 21 and the elementisolation regions 22 simultaneously.

In the present example, the gate electrode 24 is formed of polysilicon,but it is not limited to this material. For example, it may be made of atwo-layer film consisting of a polysilicon film and a high-melting pointmetal silicide film, such as titanium silicide, tungsten silicide orcobalt silicide, or a two-layer film consisting of a polysilicon filmand a high-melting point metal film, such as tungsten, or a single layerconsisting of a high melting-point metal, such as titanium nitride ortungsten.

In the present embodiment, a sidewall insulating film of the gateelectrode 24 is formed of a two-layer film consisting of a thermal oxidefilm (the silicon oxide film 26) and a silicon nitride film (theinsulating sidewall 29). The sidewall insulating film of the gateelectrode 24 may also be made of a two-layer film consisting of a CVD(chemical vapor deposition) oxide film and a silicon nitride film, asingle layer film of a CVD oxide film or a single layer film of asilicon nitride film.

Next, as shown in FIG. 1(b), using the gate electrode 24 as a mask, BF₂ions are implanted so that portions 31 in the p-type silicon substrate,which are to become source/drain regions, are made amorphous. Theimplantation of BF₂ ions having the opposite conductivity to the sourceand the drain also has a function of forming a halo region 32, whichsuppresses growth of a depletion layer to reduce the short-channeleffect. At this time, BF₂ ions are implanted at the angle of inclinationof 0-60° C. relative to the silicon substrate with the implantationenergy in the range of 5 keV-130 keV such that the resulting haloregions 32 as diffusion layer regions contain the impurity at theconcentration of 5×10¹⁷/cm³-1×10¹⁹/cm³.

In the present embodiment, BF₂ ions are used in order to make thesurface of the p-type semiconductor substrate 21 amorphous, however, thepresent invention is not limited to this. For example, B ions, In ions,Si ions or Ar ions may also be implanted. However, a B ion is lighterthan a BF₂ ion. Thus, with implantation of the B ions at an amount justattaining the above impurity concentration, it is difficult to make thesurface of the p-type semiconductor substrate amorphous. Therefore, inthe case where B ions are used, it is required to implant molecules oflarge mass, such as Si or Ar ions, before or after the implantation of Bions. The inclination angle and the implantation dose of B ions are thesame as in BF₂ ions. B ions and In ions are implanted at an energy of 5keV-30 keV, 5 keV-200 keV, respectively.

Then, polysilicon is deposited on the entire surface of the p-typesemiconductor substrate 21 including the portions that have been madeamorphous by the implantation of the impurities. In the presentembodiment, polysilicon was deposited by a low pressure CVD method in anatmosphere having an oxygen concentration of 1 ppm or lower. Asmentioned above, the p-type semiconductor substrate 21 made amorphous bymeans of the implantation of the impurities prevents a silicon filmdeposited in this step by the CVD method from growing epitaxiallyinheriting the crystal orientation of a silicon substrate that is thep-type silicon substrate 21.

If the deposition of polysilicon is attempted without implantation ofthe above impurities in the silicon substrate 21, then a silicon filmgrows epitaxially succeeding the crystal orientation of the siliconsubstrate 21. As a result, the variations in the thickness of theepitaxial film will affect the junction depth because the diffusion rateof the impurities in the epitaxial growth region (namely, single-crystalsilicon) is remarkably lower than that in polysilicon.

However, if the p-type semiconductor substrate 21 is made amorphous inadvance by implanting the impurities thereinto, it is possible to formpolysilicon during the silicon deposition process by the CVD method.Using the fact that the diffusion rate of the impurities in polysiliconis higher than that in single-crystal silicon (the epitaxial growthfilm), it is possible to form a shallow junction that is hardly affectedby the variations in the film thickness of the deposited polysilicon.

In the deposition of the polysilicon film of the present embodiment, itis important to deposit it in a manner so as not to form native oxide atan interface between the surface of the active region of the p-typesemiconductor substrate 21 and the polysilicon film deposited. In thecase where native oxide 43 is formed at an interface between the surfaceof an active region of a semiconductor substrate 41 and a polysiliconfilm 42 deposited, as shown in FIG. 2, this native oxide film 43 willserve as a diffusion barrier later when diffusing impurities serving asdonors or acceptors into the semiconductor substrate 41 by thermaldiffusion, which process is preceded by the introduction of theimpurities into the polysilicon film 42 by the ion implantation process,so that the native oxide 43 hinders uniform diffusion of the impurities.As a result, the source/drain junction depth becomes nonuniform, whichwould cause variations of the transistor characteristics. A referencenumeral 44 indicates a source/drain region.

In the present embodiment, use of a low pressure CVD (LPCVD) systemequipped with a preliminary vacuum evacuation chamber, a nitrogen purgechamber in which the dew point is kept at −100° C., and a depositionfurnace enables the polysilicon film to be deposited without growingnative oxide at the interface between the surface of the active regionof the p-type semiconductor substrate 21 and the polysilicon filmdeposited.

Specifically, immediately before the deposition of the polysilicon film,the entire surface of the p-type silicon substrate or wafer 21 is washedwith a hydrofluoric acid solution to remove native oxide if any. Afterthat, the resultant silicon wafer is conveyed to the preliminary vacuumevacuation chamber. Next, an atmosphere in which the wafer was conveyedis evacuated once and then replaced with a nitrogen ambient, and thewafer is conveyed to the nitrogen purge chamber in which the dew pointis always kept at −100° C. The role of this nitrogen purge chamber is tocompletely eliminate water molecules adsorbed onto the surface of thewafer by nitrogen purge. Water molecules adsorbed onto the surface ofthe wafer cannot be eliminated under vacuum and experiments revealedthat nitrogen purge can eliminate such water molecules completely.

In an ordinary LPCVD system, a wafer is conveyed to a deposition furnacewith water molecules adsorbed onto the surface of the wafer. Usually,deposition of a polysilicon film is carried out at a temperature in therange of about 550° C. to 700° C. For that reason, when the wafer isconveyed to a high-temperature furnace, before a polysilicon film isdeposited, oxygen components in the adsorbed water molecules react withthe silicon wafer thereby forming native oxide on the surface of thesilicon wafer. That is why native oxide exists at an interface betweenthe surface of the active region of the p-type semiconductor substrate21 and the polysilicon deposited.

On the other hand, in the LPCVD system used in the present embodiment,the silicon wafer is conveyed to the deposition furnace after theadsorbed water molecules are completely eliminated in the nitrogen purgechamber keeping the dew point at −100° C., as described above.Therefore, it is possible to deposit a polysilicon film without theformation of native oxide. In this way, a polysilicon film having athickness of about 30 nm-500 nm was deposited in the present embodiment.

Thereafter, as shown in FIG. 1(c), the deposited polysilicon is etchedback so as to form polysilicon sidewalls 33. In this case, the presenceof the insulating film 30 that is a protective layer for the p-typesemiconductor substrate 21 and the element isolation regions 22 makes itpossible to etch back the polysilicon layer without giving etchinginduced damage to the p-type semiconductor substrate 21.

Next, as shown in FIG. 1(d), high-concentration n-type impurity ions areimplanted into the polysilicon sidewalls 33, and then the n-typeimpurity ions are diffused also into the p-type semiconductor substrate21 thus forming source/drain regions 34 including the polysilicon sidewalls and portions defining junctions in the p-type semiconductorsubstrate 21. Halo regions 32 are formed at a boundary between thejunction-defining portions in the source/drain regions 34 and thechannel region in the semiconductor substrate 21. In this case, theabove thermal treatment is performed sufficiently so that the impurityions are diffused to the extent of the width of the polysilicon sidewall 33, whereby a source/drain elevated type semiconductor device iscompleted.

As described above, in the present embodiment, the gate oxide film 23,the gate electrode 24, and the gate cap insulating film 25 are stackedin this order and the insulating sidewall 29 is then formed on bothsides thereof in the active region defined by the element isolationregions 22. Then, BF2 ions are implanted into the portions 31 to becomethe source/drain regions in the p-type semiconductor substrate 21, so asto make the top surface of the p-type semiconductor substrate 21amorphous. Since the top surface of the p-type semiconductor substrate21 is made amorphous, polysilicon which favors the formation of ashallow junction is deposited, without the occurrence of the epitaxialgrowth of the single-crystal silicon, when forming the elevatedsource/drain regions.

Further, when the surface of the p-type semiconductor substrate is madeamorphous, BF₂ ions having the opposite conductivity to the source/drainare used. Thus, it is possible to form the halo regions 32 having thefunction of preventing the short-channel effect, while suppressing theextension of the depletion layer.

Furthermore, before polysilicon is deposited on the p-type semiconductorsubstrate 21 so as to elevate the source/drain, the wafer is passedthrough a preliminary vacuum evacuation chamber and then a nitrogenpurge chamber in which the dew point is kept at −100° C. In this way,water molecules adsorbed onto the surface of the wafer are eliminatedcompletely. Therefore, native oxide does not grow at the interfacebetween the surface of the active region of the p-type semiconductorsubstrate 21 and the deposited polysilicon film. Accordingly, whendiffusing the impurities, which have been introduced to the polysiliconside walls 33, into the p-type semiconductor substrate 21 by thermaldiffusion to form the source/drain regions 34, it is possible to preventa nonuniform junction depth of the source/drain from occurrence due tonative oxide serving as the diffusion barrier. In this way, it ispossible to achieve a uniform shallow junction between the source/drainregions 34 and the p-type semiconductor substrate 21.

In the present embodiment, the source/drain implantation is conductedimmediately after forming the polysilicon sidewalls 33. However, anannealing process may be added before the source/drain implantationprocess. The annealing process recovers defects in the p-typesemiconductor substrate 21 that occurred during the implantation of BF₂ions for making the p-type semiconductor substrate 21 amorphous, andsuppresses diffusion of n-type impurities in the semiconductor substrate21 during the thermal treatment for the formation of the source/drainregions 34. Therefore, it becomes possible to form a shallower junction.

Moreover, the present invention has the following effects andadvantages:

The transistor in the above described embodiment has a gate length of0.15 μm. As the scale down of elements advances to their gate lengths of0.1 μm or lower, BF₂ ions, which are directed obliquely using the gateelectrode as a mask, will be implanted into the whole channel region. Asa result, an implantation process which is conducted in order to controlthe threshold voltage will become unnecessary. In short, in the case ofa minute element with a gate length of not more than 0.1 μm,implantation of BF₂ ions for suppressing the short-channel effect andthe epitaxial growth can serve as an implantation process forcontrolling the threshold voltage also, and thus the process steps canbe reduced. Thus, the advantages of the present invention become eminentas the scale down of elements advances.

Although the present embodiment has been described using as an examplean n-channel MOSFET, a p-channel MOSFET can also be formed.

In the present embodiment, implantation of BF₂ ions for making thesurface of the p-type semiconductor substrate amorphous is performedafter forming the insulating sidewalls 29 on the sides of the gateelectrode 24, but it is not limited to this. For example, theimplantation may be performed after forming the gate electrode 24.

In the present embodiment, the wafer is passed through the nitrogenpurge chamber keeping the dew point at −100° C. and water moleculesadsorbed onto the surface of the wafer are removed so as not to grownative oxide at the interface between the surface of the active regionof the p-type semiconductor substrate 21 and the deposited polysiliconfilm. However, the method for preventing the growth of the native oxideis not limited to this. What is essential is to deposit polysiliconunder an ambient having the oxygen concentration of not more than 1 ppm.

Second Embodiment

FIG. 3 is a sectional view of an n-channel MOSFET fabricated by theproduction method for an n-channel MOSFET described in the firstembodiment. In FIG. 3, on an active region delimited by elementisolation regions 52 on a p-type semiconductor substrate (or a p-typewell region of the semiconductor substrate) 51, a gate oxide film 53, agate electrode 54, and a gate cap insulating film 55 are stacked.Further, a thermal oxide film 56 is disposed on both sides of the gateelectrode 54. Moreover, an insulating sidewall 57 is formed on bothsides of a laminate consisting of the gate oxide film 53, the thermaloxide films 56 and the gate cap insulating film 55.

Further, an insulating film 58 is disposed on the element isolationregions 52 and extends toward the active region on the p-typesemiconductor substrate 51, and polysilicon sidewalls 59 are disposedoutside of the insulating sidewalls 57. The polysilicon sidewalls 59 hadn-type high-concentration impurities implanted, and the impurities havebeen diffused in the p-type semiconductor substrate 51. In this way,elevated source/drain regions are constituted of the polysiliconsidewalls 59 and the n-type high-concentration impurity layers 60 formedunder the insulating layers 58 in the active region. Further, betweeneach source/drain region 60 in the active region and the channel regionin the p-type semiconductor substrate 51, halo regions 61 that arep-type impurity layers are disposed.

In the above structure, because the source/drain regions 59 are elevatedand also the depth of the junction 60 between the source/drain regionsand the semiconductor substrate 51 is shallow, even if the thickness ofthe insulating sidewall 57 is set to a specified value or more enough tosuppress increases in leak current and capacitance between the gateelectrode 54 and each of the polysilicon sidewalls 59, the short-channeleffect is suppressed without increasing the source-drain resistance.

In a conventional n-channel MOSFET having no halo regions, as shown inFIG. 4, the relationship between the film thickness “a” of a gateelectrode insulating sidewall 66 formed on side surfaces of the gateelectrode 65, and the junction depth “b” of source/drain regions 67 isapproximately 0.7 to 1, provided that the source/drain regions do notconstitute an offset structure with respect to the channel. That is,once the film thickness “a” of the gate electrode insulating sidewall 66is determined, a minimum value of the junction depth “b” isautomatically determined.

Incidentally, the short-channel effect dominantly depends on thejunction depth “b” of the source/drain regions 67. To suppress theshort-channel effect under a certain design rule, the junction depth “b”is univocally determined, and hence the film thickness “a” of the gateelectrode insulating sidewall 66 is univocally determined. That is,there is no design freedom. Contrary to this, in the case of then-channel MOSFET of the present embodiment, the short-channel effect canbe controlled by the halo regions 61, and thus it is possible to providethe insulating sidewalls 56, 57 of the gate electrode with designfreedom in film thickness.

For example, in the present embodiment, a transistor with a gate lengthof 0.15 μm is designed. For that gate length, in a conventionaltransistor shown in FIG. 4, it is required that the junction depth “b”of the source/drain regions 67 be made as shallow as about 30 nm tosuppress the short-channel effect. Thus, the film thickness “a” of thegate electrode insulating sidewall 66 is logically about 20 nm or less.On the other hand, in the transistor of the present embodiment, in thecase where the impurity concentration of the hallo regions 61 is set to5×10¹⁷/cm³-1×10¹⁹/cm³ for example, the film thickness of the insulatingsidewalls 56, 57 of the gate electrode can be set to a thickness ofabout 70 nm. In other words, even if a deeper junction is formed, theshort-channel effect can be suppressed. In this case, the capacitancebetween the gate electrode 54 and each of the elevated source/drain 59per unit gate width (1 μm) can be reduced to about 0.16 fF, in contrastto a conventional value of 0.37 fF.

Accordingly, by reducing the parasitic capacitance between the gateelectrode 54 and the source/drain 59, the capacitance required forcharging the n-channel MOSFET in the present embodiment is reduced.Thus, a circuit designed using the n-channel MOSFET of the presentembodiment has an improved operation speed.

In the n-channel MOSFET of the present embodiment, the impurityconcentration of the p-type semiconductor substrate 51 was5×10¹⁶/cm³-1×10¹⁸/cm³, and the impurity concentration of the n-typesource/drain regions 60 was 1×10²⁰/cm³-1×10²²/cm³. The height of thegate electrode 54 and that of the elevated source/drain 59 were 200 nm.The gate electrode insulating sidewall was made up of a 10 nm thickthermal oxide film (silicon oxide film) 56 and a 60 nm thick insulatingsidewall (silicon nitride film) 57. For comparison, in the conventionaln-channel MOSFET, the gate electrode insulating sidewall 66 was formedof a 10 nm thick silicon oxide film and a 15 nm thick silicon nitridefilm. In the case of the conventional transistor also, the heights ofthe gate and the elevated source/drain regions were equal to those ofthe transistor in the present embodiment, and the capacitances werecompared.

Third Embodiment

FIG. 5 is a sectional view of an n-channel MOSFET different from that inFIG. 3. In FIG. 5, on each of active regions into which a p-typesemiconductor substrate (or a p-type well region) 71 is sectioned orplotted by element isolation regions 72 on the p-type semiconductorsubstrate (or the p-type well region) 71, a gate oxide film 73, a gateelectrode 74, and a gate cap insulating film 75 are provided in astacked manner. A thermal oxide film 76 is disposed on both sides of thegate electrode 74. Moreover, an insulating sidewall 77 is formed on bothsides of a laminate consisting of the gate oxide film 73, the thermaloxide film 76 and the gate cap insulating film 75.

Further, an insulating film 78 is formed on the p-type semiconductorsubstrate 71 from the element isolation region 72 toward the activeregion, and a polysilicon sidewall 79, into which the n-typehigh-concentration impurities have been implanted, is disposed outsideof the insulating sidewalls 77. The polysilicon sidewall 79 constitutesan elevated portion of a source/drain region. In the present embodiment,the length “c” on an upper side of the polysilicon sidewall 79 in thelongitudinal direction of the gate electrode 74 (namely, the length in adirection perpendicular to the transistor gate width direction=thelength in the transistor gate length direction) is longer than thedistance between the insulating sidewall 77 and the element isolationregion 72 “d”. In the active region, source/drain regions 80 that aren-type impurity layers are formed. Between a channel region in thep-type semiconductor substrate 71 and each of the source/drain regions80 is provided a halo region 81, which is a p-type impurity layer.

As described above, in the present embodiment, the width of thesource/drain region 80 inside the semiconductor substrate 71 isshortened, as compared with the n-channel MOSFET of the secondembodiment (for example, to 1/9). Therefore, an increase in thecapacitance between the source/drain region 80 and the p-typesemiconductor substrate 71 or the p-type well region 71 of thesemiconductor substrate due to the presence of the halo region 81 can bereduced (for example, to 1/9). Thus, it is possible to suppress anincrease in the capacitance. That is, according to the presentembodiment, the operation speed is improved as compared with then-channel MOSFET of the second embodiment.

What is claimed is:
 1. A method for producing a semiconductor device,comprising the steps of: sectioning a surface of a substrate or wellregion of first conductive type to form an active region and thenforming a gate oxide film on the active region; forming a gate electrodeon the gate oxide film; forming insulating sidewalls on side surfaces ofthe gate electrode; implanting ions into a surface of the semiconductorsubstrate or well region at portions of the active region that are to besource/drain regions, to thereby make theses portions amorphous;depositing a polycrystalline conductive film on the surface of thesemiconductor substrate or well region formed with the gate oxide film,the gate electrode and the insulating sidewalls; performing etch back onthe polycrystalline conductive film to form conductive sidewalls on sidesurfaces of the insulating sidewalls; implanting high-concentrationimpurities of second conductive type into the conductive sidewalls; anddiffusing the high-concentration impurities of second conductive typeinto the semiconductor substrate or well region by a thermal treatmentto thereby form the source/drain region.
 2. The method for producing asemiconductor device according to claim 1, wherein the ions implantedinto the surface of the active region are of the first conductive typeand at an impurity concentration higher than that of the firstconductive type semiconductor substrate or well region.
 3. The methodfor producing a semiconductor device according to claim 1, wherein thedeposition of the polycrystalline conductive film is carried out in anambient having an oxygen concentration of 1 ppm or lower.
 4. Asemiconductor device comprising a gate insulating film and a gateelectrode stacked in this order on a substrate or well region of firstconductive type, sidewall insulating films disposed on side surfaces ofthe gate electrode, a channel region formed in the semiconductorsubstrate or well region beneath the gate electrode, and source/drainregions of second conductive type elevated to above the semiconductorsubstrate or well region from both sides of the channel region, thesource/drain regions being electrically isolated from the gate electrodeby the gate insulating film and the sidewall insulating films,characterized in that: the semiconductor substrate or well region hasdiffusion regions of the first conductive type formed between thesource/drain regions and the channel region, the diffusion regionshaving an impurity concentration higher than that of the semiconductorsubstrate or well region.
 5. The semiconductor device according to claim4, wherein the impurity concentration of the first conductive typediffusion regions is 5×10¹⁷/cm³-1×10¹⁹/cm³.
 6. The semiconductor deviceaccording to claim 4, wherein the source/drain regions on the surface ofthe semiconductor substrate or well region are delimited by elementisolation regions; and the elevated source/drain region on thesemiconductor substrate or well region has, on an upper side thereof, alength (c) in a transistor gate length direction that is longer thandistance (d) between the sidewall insulating film and the elementisolation region.
 7. The semiconductor device according to claim 4,wherein the elevated second conductive type source/drain regions aremade of polysilicon.
 8. The semiconductor device according to claim 4,wherein each of the elevated source/drain regions has a portion that isin contact with the corresponding side wall insulating film at a levelabove the substrate or well region.